This invention relates to electro-optical detectors and in particular to amplifiers for interfacing with electro-optical detectors, such as photovoltaic detectors.
Many modem systems rely on electro-optical detectors, or sensors, to sense a portion of the electromagnetic spectrum. These systems might include telecommunications systems, fiber-optic systems, imaging systems, cameras, and other commercial and military systems. The electro-optical sensors of these systems can be critical components in determining performance, sensitivity, cost, and dynamic range of the overall system.
To achieve a very high level of performance, many modem electro-optical sensors include two primary functional components. The first component is a detector element or detector array. One detector element commonly used is a photovoltaic detector element. The second functional component is the readout multiplexer.
For electro-optical sensors operating in the visible spectrum and up to approximately 1.0 xcexcm wavelength radiation, silicon is commonly used to fabricate both the detector (e.g., a single detector element or an array of detector elements) and the readout multiplexer. For optical sensors operating at significantly shorter or longer wavelengths, alternative semiconductor materials may be selected for the detector to provide more efficient sensitivity for the desired region of the electromagnetic spectrum. In this case, it may be desirable to use different materials to fabricate the detector and the readout multiplexer, since the readout multiplexer can still be fabricated in silicon.
Electrical signals from individual detector elements are processed by electronics signal chains, which have become increasingly sophisticated in modern electro-optical sensors. The signal chains are now designed to optimize the impedance interface to the detector elements; the integration of the electrical signals; the noise performance of the sensor; and the signal storage, multiplexing, and processing to an optimized systems interface.
FIG. 1A is a circuit diagram and FIG. 1B is a cross-sectional side view of a typical pn junction photovoltaic detector element 10. As shown in FIG. 1A, detector element 101 is a diode structure including an anode 11 and a cathode 12. A terminal 13 is electrically coupled to anode 11, and a terminal 14 is electrically coupled to cathode 12. Detector element 10 may be fabricated by diffusing a p-type region 15 into an n-type semiconductor 16, thereby forming a pn junction as shown in FIG. 1B. Since detector element 10 is a diode structure that is responsive to illumination, detector element 10 is also called a photodiode.
In electro-optical systems, an electromagnetic image is spatially sampled in units called pixels. Detector element 10 can be used to sample a single pixel at a time. Thus, detector element 10 is also sometimes referred to as a pixel. Depending on the application and the format of detector array, the image may or may not be scanned. If the image is scanned, it may be scanned in one dimension or in two dimensions. For example, to sample a line of an electro-magnetic image, a line array of detector elements 10 is provided, or the image is scanned across the single detector element 10.
FIG. 2A is a circuit diagram and FIG. 2B is a perspective view of a typical pn junction photovoltaic detector array 20. In FIG. 2A, detector array 20 includes four detector elements 10, each with terminals 13 and 14. Typical line arrays of this type in current systems may include as many as 512, or more, detector elements 10. Individual detector elements 10 are fabricated in close proximity to each other in the necessary quantity to support the system application. In FIG. 2B, four p-type regions 15 (one for each detector element 10) are shown arranged in a line and diffused into n-type semiconductor 16. Sampling of a two-dimensional image can be accomplished by fabrication of a plurality of detector elements 10 arranged in a two-dimensional array, also called a staring array. Typical two-dimensional arrays in current systems may include 1024xc3x971024, or more, detector elements 10.
FIG. 3 is a graphical illustration of a current-voltage (IV) characteristic of pn junction photovoltaic detector element 10 of FIG. 1A under illumination. The right and left halves of the diagram are referred to as the forward bias (FB) and reverse bias (RB) regions, respectively. Under forward bias, the zero current intercept, also called the forward voltage (VF), of detector element 10 is a function of the illumination level. Similarly, under reverse bias, the reverse bias current is also a function of the illumination level. The reverse bias current, however, may also include a junction leakage current component and, under high reverse bias, a reverse bias breakdown current component.
Depending on material quality and properties, the magnitudes of the leakage current and/or the reverse bias breakdown current may be as large as, or larger than, the detector element photocurrent, which is the signal of interest. The extraneous leakage and reverse bias breakdown currents may degrade performance and dynamic range of the electro-optical sensor.
For a detector with a single detector element 10, it is reasonable to interface between the readout multiplexer and detector element 10 using wires or printed circuit board traces. In one-dimensional line arrays or two-dimensional staring arrays, however, the detector element count may be as large as 512 detector elements 10, or even over one million detector elements 10, respectively. In these cases, wire and circuit board trace interfaces are unrealistic, and it is desirable to have the readout multiplexer of the electro-optical sensor in close physical proximity to detector elements 10 to facilitate electrical coupling of detector elements 10 to the readout multiplexer.
Direct electrical coupling of detector elements 10 to the readout multiplexer allows the sizes of detector elements 10 to be small, reducing the overall size of the detector array. Integrated circuit wire bonding and bump bonding techniques have been employed to achieve such electrical interfaces. FIG. 4 is a perspective illustration of an electro-optical sensor 40 including an electro-optical detector 41 in close proximity to an integrated circuit readout multiplexer 42. Detector 41 includes a plurality (i.e., an array) of detector elements 10, each of which is coupled to an electronics signal chain for processing the signal from each detector element 10.
FIG. 5 is a circuit diagram of an array 50 of four detector elements 10 (i.e., photodiodes) each coupled to an integrating amplifier 51. Each integrating amplifier 51 includes, due to materials and manufacturing variations, a unique input offset voltage (labeled Vos1, Vos2, Vos3, and Vos4, respectively) shown explicitly coupled between terminal 13 of each detector element 10 and the input of each integrating amplifier 51.
FIG. 6A is a graphical illustration of a current-voltage (IV) characteristic for array 50 of FIG. 5, for a large input offset voltage distribution. The relatively large variation in the values of the input offset voltages Vos1, Vos2, Vos3, and Vos4 of each integrating amplifier 51 is shown for illustration purposes. The effect of variations in the input offset voltages of integrating amplifiers 51 is to cause each detector element 10 to operate at a different bias point on its IV curve. The current from each detector element 10 will thus show an offset variation that is dependent on the IV characteristic of the detector element 10 and the magnitude of the input offset voltage distribution from integrating amplifiers 51. These offset currents introduce variations in the output signals for each detector element 10. In some cases, these variations can represent a significant portion of the dynamic range of the signal levels of detector elements 10.
Input offset voltages Vos1, Vos2, Vos3, and Vos4 of integrating amplifiers 51 can also affect the noise performance of respective detector elements 10. Zero-biasing detector elements 10 can, for example, optimize the 1/f noise performance of detector elements 10. High reverse bias voltage levels can produce higher leakage currents, higher Shot noise, and higher 1/f noise current levels.
For optimum detector array performance, integrating amplifiers 51 with adjustable input voltage levels and a very low input offset voltage distribution are desirable. FIG. 6B is a graphical illustration of a current-voltage (IV) characteristic for array 50 of FIG. 5, for a very low input offset voltage distribution. For uniform diode characteristics, the fight input offset voltage distribution would result in biasing of all four detector elements 10 at a unique bias point, thus producing a uniform output current as desired for optimum electro-optical sensor design.
The selection of a bias point (in the reverse bias region, or at zero bias) of detector elements 10 is made to optimize the performance of each detector element 10 and of the overall system. This xe2x80x9czero-biasingxe2x80x9d of detector elements 10 can remove the dark current component from the current of each detector element 10. Since dark current is a function of the temperature of each detector element 10, zero-biasing can remove the need for temperature stabilization of the detector array. In addition, the 1/f noise of each detector element 10 can be reduced by providing an appropriate bias.
A variety of designs for integrating amplifiers 51 have been proposed to achieve the IV characteristic of FIG. 6B. The designs, however, have varied in their ability to generate both a controlled input offset voltage level and a low input offset voltage distribution. FIG. 7A is a circuit diagram of one integrating amplifier 51 coupled to one detector element 10. FIG. 7B is a circuit diagram of integrating amplifier 51 implemented as a differential amplifier 71 in a reset integrator configuration. In FIG. 7B, terminal 14 of detector element 10 is coupled to a detector reference voltage (DET_REF). Terminal 13 of detector element 10 is coupled to the inverting input (xe2x88x92) of differential amplifier 71. The non-inverting input (+) of differential amplifier 71 is coupled to an amplifier reference voltage (AMP_REF). A feedback capacitor 72 (Cf) is coupled in parallel with a switch 73, controlled by a signal RESET, between the output of differential amplifier 71 and the inverting input (xe2x88x92) of differential amplifier 71.
In FIG. 7B, current from detector element 10 de-biases the inverting input (xe2x88x92) of differential amplifier 71. The high, inverting gain of differential amplifier 71 causes the output of differential amplifier 71 to oppose the inverting input voltage change, thus generating a changing voltage across feedback capacitor 72 (Cf). This maintains the inverting input (xe2x88x92) of differential amplifier 71 at a nearly constant voltage, while the output voltage changes in response to the input current from detector element 10. Switch 73 is used to reset integrating amplifier 51 and to return the input and output voltages to a reset potential.
FIG. 8 is a timing diagram for integrating amplifier 51 of FIG. 7B. When signal RESET, which controls switch 73 of FIG. 7B, is at a potential Von, the output of integrating amplifier 51 is equal to the reset potential AMP_REF. After signal RESET transitions to a potential Voff, the current from detector element 10 pulls the inverting input (xe2x88x92) of differential amplifier 71 positive, causing the output of integrating amplifier 51 to go negative. The current from detector element 10 is given by Idet=Cf(dV/dt), where dV is the change in output voltage over the integration time and dt is the integration time. The magnitude of the negative voltage output signal from integrating amplifier 51 is thus a function of the current level flowing from detector element 10, the integration time, and the size of feedback capacitor 72 (Cf).
A variety of differential and single-ended implementations of integrating amplifier 51 are possible. FIG. 9 is a circuit diagram of a CMOS embodiment of integrating amplifier 51 of FIG. 7B. A p-type MOSFET 91 acts as a current source for differential amplifier 71. The source and body of MOSFET 91 are coupled to a positive reference voltage VPOS. The gate of MOSFET 91 is coupled to receive a biasing signal AMP_CS1. The drain of MOSFET 91 is coupled to the sources of a p-type MOSFET 92 and a p-type MOSFET 93. MOSFETs 92 and 93 form a common source pair for differential amplifier 71. The bodies of MOSFETs 92 and 93 are coupled to VPOS. The gate of MOSFET 92, which is the inverting input (xe2x88x92) of differential amplifier 71, is coupled to terminal 13 of detector element 10. The current flowing in detector element 10 is denoted Idet. The gate of MOSFET 93, which is the non-inverting input (+) of differential amplifier 71, is coupled to amplifier reference voltage AMP_REF.
An n-type MOSFET 94 and an n-type MOSFET 95 serve as loads in differential amplifier 71. The sources and bodies of MOSFETs 94 and 95 are coupled to a negative reference voltage VNEG. The gates of MOSFETs 94 and 95 are coupled together. The drain of MOSFET 94 is coupled to the gate of MOSFET 94 and to the drain of MOSFET 93. The drain of MOSFET 95 is coupled to the drain of MOSFET 92, which is the output of differential amplifier 71 and of integrating amplifier 51.
As in FIG. 7B, feedback capacitor 72 (Cf) is coupled between the inverting input (the gate of MOSFET 92) of differential amplifier 71 and the output (the drain of MOSFET 92) of integrating amplifier 51. An n-type MOSFET 96, with a gate driven by signal RESET, serves as switch 73 in FIG. 9. MOSFET 96 is coupled in parallel with feedback capacitor 72, with one terminal coupled to the gate of MOSFET 92 and one terminal coupled to the drain of MOSFET 92.
Although the CMOS implementation of integrating amplifier 51 in FIG. 9 allows adjustable biasing of detector element 10, the implementation exhibits an input offset voltage distribution that is a function of the threshold voltages of MOSFETs 92, 93, 94, and 95. A typical input offset voltage distribution (one sigma) for the implementation of FIG. 9 may be several millivolts, which is larger than desired for optimum performance of an electro-optical detector.
Various circuits have been proposed to reduce the input offset voltage distribution further. FIG. 10A is a circuit diagram including an alternative embodiment of integrating amplifier 51 of FIG. 7A. An auto-zero coupling capacitor 101 (labeled CAz) is coupled between terminal 13 of detector element 10 and the inverting input of a single-ended inverting amplifier 81. Switch 73, controlled by signal RESET, is coupled between the output of inverting amplifier 81 and the inverting input of inverting amplifier 81. A second switch 102, also controlled by signal RESET, is coupled between terminal 13 of detector element 10 and a reference voltage Vzero. Feedback capacitor 72 (Cf) is coupled between the output of inverting amplifier 81 and terminal 13 of detector element 10. The output of inverting amplifier 81 also serves as the output of integrating amplifier 51.
Resetting integrating amplifier 51 of FIG. 10A closes switches 73 and 102. This equilibrates the potentials of the inverting input of inverting amplifier 81 and the output of inverting amplifier 81. It also sets the input of integrating amplifier 51 (terminal 13 of detector element 10) to reference voltage Vzero. This stores the input offset voltage error across CAz capacitor 101. At the end of the reset process, switches 73 and 102 open. The input offset voltage error is still stored across CAz capacitor 101, and feedback capacitor 72 (Cf) controls the bias of the inverting input of inverting amplifier 81 as described above with reference to FIG. 7B.
FIG. 10A also shows a sample and hold stage 103 coupled between the output of integrating amplifier 51 and the input of an output amplifier 104. Sample and hold stage 103 includes a switch 105, which samples the output voltage of integrating amplifier 51 and stores the value on a capacitor 106 (labeled CSH). Output amplifier 104 drives the signal sampled and held on capacitor 106. FIG. 10B is a block diagram of the circuit diagram of FIG. 10A. In FIG. 10B, an electronics signal chain 108 includes detector element 10, integrating amplifier 51 configured for auto-zero biasing, sample and hold stage 103, and output amplifier 104.
Auto-zero biasing, such as that implemented in FIG. 10A and FIG. 10B, can help reduce the input offset voltage distribution of the various integrating amplifiers 51 in the electronics signal chains of an array of detector elements 10. The distribution, however, is still significant, since it is largely due to variations in the charge pumping that occurs upon opening and closing switches 73 and 102 (which may be MOS switches) when resetting feedback capacitor 72 (Cf) and auto-zero coupling capacitor 101 (CAz). In addition, single-ended amplifiers, such as inverting amplifier 81, cannot be locally referenced. This has limited the performance of electro-optical sensors. Accordingly, an improved auto-zero biasing amplifier and technique is desirable for optimal electro-optical sensor performance.
In accordance with an embodiment of the present invention, an electronics signal chain for an electro-optical detector includes an integrating auto-zero amplifier circuit coupled to a detector element responsive to illumination. A first terminal of the detector element is coupled to a first input of the auto-zero amplifier circuit. A second terminal of the detector element is coupled to a second input of the auto-zero amplifier circuit, so that the auto-zero amplifier circuit is locally referenced to the detector element.
The auto-zero amplifier circuit includes a first amplifier, a second amplifier, and a first coupling capacitor. The first coupling capacitor is coupled between a first output of the first amplifier and a first input of the second amplifier. A first input and a second input of the first amplifier are respectively coupled to the first input and the second input of the auto-zero amplifier circuit. The first amplifier of the auto-zero amplifier circuit may be a low noise, fixed gain amplifier. The second amplifier of the auto-zero amplifier circuit may be a high gain amplifier.
In an exemplary embodiment of a method of auto-zeroing an integrating amplifier circuit, a first terminal of a detector element is decoupled from the integrating amplifier circuit, and a first stage of the integrating amplifier circuit is locally referenced to a second terminal of the detector element. An auto-zero voltage for the integrating amplifier circuit is stored between the first stage of the integrating amplifier circuit and a second stage of the integrating amplifier circuit. The auto-zero voltage may be stored differentially using one or more storage elements (e.g., capacitors).
A two-stage auto-zero amplifier circuit in accordance with an embodiment of the present invention provides an improved interface to a photovoltaic electro-optical detector element and improves the performance of a stage in the electronics signal chain that is used to process signals from the detector element. The incorporation of the first low noise, fixed gain amplifier improves the performance of the auto-zero amplifier circuit in many areas by a function of the first amplifier""s fixed gain. This new approach to designing auto-zero amplifier circuits for electro-optical detectors is expected to provide a more robust interface to the detector elements. As such, this approach is expected to realize higher yields, and lower costs, as it is less sensitive to detector material quality and defects.